1. Field of the Invention
The present invention relates to an image processing device, image processing method and distribution medium, and particularly to an image processing device and method, and distribution medium that are low-cost wherein the device has a simple construction which is able to perform image processing.
2. Description of the Prior Art
FIG. 1 shows a sample configuration of an image processing device. Video camera 1 photographs a subject, which is not illustrated, and outputs the image data of that subject to image processor 2 and CPU 5. Image processor 2 stores the image data that was input from video camera 1 memory 11. If CPU 5 instructs arithmetic unit 12 of image processor 2 to perform a stipulated operation, arithmetic unit 12 applies the stipulated operation corresponding to this instruction to the image data stored in memory 11 and outputs the resulting computation data to the graphics processor 3.
Graphics processor 3 stores the computation data that was input from image processor 2 in memory 21. CPU 5 controls display data generator 22 of graphics processor 3 to generate display data from the computation data stored in memory 21. The display data that was generated in graphics processor 3 is output and displayed on CRT 4.
CPU 5 also receives a supply of data that is output from video camera 1 or image processor 2, executes stipulated processing as necessary, and outputs the data to image processor 2 or graphics processor 3.
If, for example, this kind of image processing device were to perform processing that applied convolution filtering to the image data that was output from video camera 1 and output the result to CRT 4 for display, the operation at this time would be, for example, as shown in the flowchart in FIG. 2. This processing is basically executed by CPU 5.
In step S1, CPU 5 receives a supply of image data corresponding to one frame from video camera 1. This image data, which can be considered as the source frame image data, consists of an HMAX, VMAX array of pixel data Csp as shown, for example, in FIG. 3. In step S1, CPU 5 also sets the convolution filter coefficients Cv[m][n]. In the example in FIG. 4, these convolution filter coefficients Cv[m][n] consist of a 3×3 array of coefficients.
Next, in step S2, CPU 5 assumes an HMAX VMAX array of pixel data as destination frame pixel data Cdp, as shown in FIG. 5, and initializes the value of pixel data Cdp[1][1] corresponding to coordinate (1,1) among them to 0. In addition, CPU 5 initializes variable j to 1 in step S3 and variable i to 1 in step S4. The variables i and j represent the horizontal coordinate (i) and vertical coordinate (j) of the source frame image (FIG. 3) and destination frame image (FIG. 5), as shown in FIG. 3 and FIG. 5. Variable i takes the values from 0 to HMAX-1, and variable j takes the values from 0 to VMAX-1.
In steps S5 and S6, the variables n and m are each initialized to 0. The variables n and m represent the horizontal coordinate (m) and vertical coordinate (n) of the convolution filter coefficients, as shown in FIG. 4. In this example, m and n each take the values from 0 to 2.
Next, in step S7, CPU 5 executes the computation indicated by the following equation.Cdp[i][j]=Cdp[i][j]+Cv[m][n]*CSP[i+m−1][j+n−1]  (1)
Now, since j=1, i=1, n=0, and m=0 have been set and the initial value of Cdp[i][j] has been set to 0, the following equation can be obtained.Cdp[1][1]=Cv[0][0]*CSP[0][0]  (2)
Next, processing advances to step S8, and CPU 5 judges whether or not variable m is less than 2. Since m=0 at this time, it is less than 2. Therefore, processing advances to step S9 where m is incremented by 1. At this time, m=1. Processing then returns to step S7, and equation (1) is computed again. The following equation is obtained as the result.Cdp[1][1]=Cdp[1][1]+Cv[1][0]*CSP[1][0]  (3)
Here, the value of Cdp[1][1] on the right hand side of equation (3) is the value obtained by using equation (2).
Processing advances to step S8, and CPU 5 again judges whether or not variable m is less than 2. Since m=1 at this time, processing advances to step S9 where m is incremented by 1. At this time, m=2. Then, processing returns to step S7, and equation (1) is computed again.
The following equation is obtained as the result.Cdp[1][1]=Cdp[1][1]+Cv[2][0]*CSP[2][0]  (4)
The processing described above results in a value that is the sum of the products obtained by multiplying the convolution filter coefficients Cv[0][0], Cv[1][0], and Cv[2][0] by the source pixel data CSP[0][0], CSP[1][0], and CSP[2][0], respectively.
Next, processing advances to step S8, and CPU 5 judges whether or not variable m is less than 2. Since m=2 at this time, the judgment result is NO, and processing advances to step S10. In step S10, CPU 5 judges whether or not variable n is less than 2. Since n=0 at this time, the judgment result is YES, and processing advances to step S11. In step S11, variable n is incremented by 1. At this time, n=1.
Then, after processing returns to step S6 where m is initialized to m=0, equation (1) is computed again in step S7. The following equation is obtained as the result.Cdp[1][1]=Cdp[1][1]+Cv[0][1]*CSP[0][1]  (5)
Next, processing advances to step S8, and CPU 5 judges whether or not variable m is less than 2. Since m=0 at this time, the judgment result is YES, and m is set to m=1 in step S9. Then, processing returns to step S7, and equation (1) is computed again. Equation (6) is obtained as the result.Cdp[1][1]=Cdp[1][1]+Cv[1][1]*CSP[1][1]  (6)
The above processing is repeated, and the equations (7) to (10) shown below are computed as the results.Cdp[1][1]=Cdp[1][1]+Cv[2][1]*CSP[2][1]  (7)Cdp[1][1]=Cdp[1][1]+Cv[0][2]*CSP[0][2]  (8)Cdp[1][1]=Cdp[1][1]+Cv[1][2]*CSP[1][2]  (9)Cdp[1][1]=Cdp[1][1]+Cv[2][2]*CSP[2][2]  (10)This completes convolution filtering in which the single pixel data CSP[1][1] is the subject pixel.
Since n=2 in step S10 at this time, the judgment result is NO, and processing proceeds to step S12. In step S12, CPU 5 judges whether or not variable i is less than HMAX-2 (in this example, since HMAX=6, CPU 5 judges whether or not variable i is less than HMAX-2=4). Since i=1 at this time, it is less than HMAX-2, and the judgment result is YES. Processing advances to step S13 where variable i is incremented by 1. At this time, i=2. Then, processing returns to step S5, and the subsequent processing is executed. That is, convolution filtering in which the pixel data CSP[2][1] is the subject pixel is executed in a similar manner as described for convolution filtering in which pixel data CSP[1][1] is the subject pixel.
Convolution filtering is performed sequentially for each pixel data in row j=1. When pixel data CSP[1][HMAX-2] (for the example in FIG. 3, this is CSP[1][4]) is reached, the judgment result in step S12 is NO, and processing advances to step S14. In step S14, CPU 5 judges whether or not variable j is less than VMAX-2 (in this example, since VMAX=6, CPU 5 judges whether or not variable j is less than VMAX-2=4). Since j=1 at this time, the judgment result is YES. Processing advances to step S15 where variable j is incremented by 1. At this time, j=2. Then, processing returns to step S4, and the subsequent processing is executed. That is, convolution filtering is executed for each pixel data in row j=2 in a similar manner as described above.
When the convolution filter coefficient computation is completed as described above for the source pixel data CSP[HMAX-2][VMAX-2] in the column for which i is HMAX-2 of the row in which j is VMAX-2, the judgment result is NO in step S14, and convolution filtering is completed.
CPU 5 supplies the data for the computation results obtained as described above to graphics processor 3. Graphics processor 3 stores the image data corresponding to one frame, which was input from CPU 5, in memory 21. Display data generator 22 transforms this image data to display data and outputs it to CRT 4 for display.
Although it was assumed in the above description that convolution filtering was executed by CPU 5, it can also be executed by image processor 2. Additionally, special-purpose hardware for executing this kind of processing can be provided separately, and this processing can also be executed by that hardware.